Conventional NAND flash memories typically multiplex input/output (I/O) lines for receiving command, address, and data signals. Some commands, such as a program (i.e., write) command, require all three different types of information to be provided to the memory device. That is, in order to program memory cells with new data, a program command is issued, then the addresses of the memory cells that will be programmed are provided, and finally, data to be programmed are provided. A confirmation command is typically issued after the data are provided to the memory indicating the end of the command. All of this information is provided to the memory using the same I/O lines.
Control signals are used to differentiate the types of signals when latching the different information into the memory. For example, typical control signals command latch enable (CLE) and address latch enable (ALE) signals are brought to a HIGH logic level to indicate to the memory device that the signals that will be latched in response to the next rising edge of a write enable (WE#) signal are either a command or an address, respectively. Thus, when the CLE signal is HIGH (and the ALE signal is LOW), the signals latched from the I/O lines in response to a rising edge of the WE# signal represent a command. In contrast, when the ALE signal is HIGH (and the CLE signal is LOW), the signals latched from the I/O lines in response to a rising edge of the WE# signal represent an address. When both the CLE and ALE signals are LOW, the signals latched from the I/O lines in response to a rising edge of the WE# signal represent data.
In programming data to the memory, the time for the program operation to complete can be divided into three general time ranges: (1) command and address writing time, (2) data loading time, and (3) programming time. Using an example of a write cycle time tWC of 35 ns (i.e., the period of the WE# signal), command and address writing time can be about 245 ns (i.e., 7.times.35 ns), programming time about 150 us, and assuming that data for a full page is being loaded (further assuming a 2 kbyte page and byte-wide I/O lines), 71.7 us (i.e., 35 ns.times.2 kbytes) for the data loading time. As illustrated by the present example, the command and address writing time is nearly negligible, but the data loading time can be almost one-third of the total time for the program operation to complete.
One approach that has been taken in improving programming bandwidth of flash memory is through multi-plane page programming. As known, a memory array of flash memory cells is often divided into a plurality of memory “planes,” for example, one memory may have a memory array divided into two memory planes, or for another memory, the memory array is divided four separate memory planes. In a multi-plane page programming operation, data are sequentially loaded to data registers for each of the memory planes, and the loaded data are then programmed to the memory planes simultaneously. In this manner, the program time, which is generally the same if one page of memory is programmed or multiple pages for multiple memory planes (one page per memory pane) are programmed, is shorter compared to sequentially programming multiple pages for multiple memory panes. A disadvantage, however, is that loading data to the data registers can take considerable time, especially in the case where full pages of data are being written for each of the memory planes.
An improvement to multi-plane programming is combining multi-plane programming with a secondary cache register, which is included in the memory in addition to the data register. Data to be programmed are initially loaded to a cache register. The data are then moved to a data register and programming of the data now in the data register begins. After programming has begun, new data can be loaded to the cache register in preparation for programming upon completion of programming the previous data. As applied to multi-page programming, data are sequentially loaded to the cache registers associated with the different memory planes. Upon completion of data loading for each of the memory planes, the data are simultaneously copied from the cache registers to the respective data registers and simultaneous memory plane programming begins. During programming, new data can be sequentially loaded for programming to the memory planes into the respective cache registers. When programming of the previous data are complete, the new data for all of the memory planes are moved from the cache registers to the respective data registers, and simultaneous programming of the new data is begun. The cache registers allows some of the data loading time to be “hidden” since data can be loaded during the time data are being programmed to the memory planes. In contrast, in multi-page programming without cache registers (i.e., using only data registers), loading of new data to be programmed cannot begin until programming of the previous data is completed.
A disadvantage of cache multi-page programming is that considerable layout area is used for the cache registers. Each of the cache registers for the memory planes is typically the same size as the corresponding data registers. As a result, the layout area devoted to registers is doubled where cache registers are included. As a result, although programming bandwidth for cache multi-page programming is improved over non-cache multi-page programming, layout area is sacrificed to provide this feature. In applications where miniaturization is a priority, doubling the layout area occupied by registers is undesirable.